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A generalized family of memristor-based voltage controlled relaxation oscillator
Recently, memristive oscillators are a significant topic in the nonlinear circuit theory where there is a possibility to build relaxation oscillators without existence of reactive elements. In this paper, a family of voltage-controlled memristor-based relaxation oscillator including two memristors is presented. The operation of two memristors-based voltage relaxation oscillator circuits is
Fractional-Order Relaxation Oscillators Based on Op-Amp and OTRA
This paper introduces closed formulas of two topologies of fractional-order relaxation oscillators. One of these topologies is based on Operational Amplifier (Op-Amp) and the other one depends on Operational Operational Trans-Resistance Amplifier (OTRA). Special cases for each topology are also provided. The advantage of these designs comes from the added extra degree of freedom presented by the
Comparison between three approximation methods on oscillator circuits
The promising capabilities of fractional-order devices challenge researchers to find a way to build it physically. Approximating the Laplacian operator sα can pave the way to emulate the fractional-order devices till its off-the-shelf appearance. This paper introduces three approximations of the Laplacian operator sα: Oustaloup, Matsuda, and Valsa by comparing their behaviors through two types of
FPGA Implementation of X- and Heart-shapes Controllable Multi-Scroll Attractors
This paper proposes new multi-scrolls chaotic systems which is called the X-shape. The purpose is to have more complex systems and flexible ranges of the chaotic behavior. The proposed X-shape is a combination between V-shape and Λ-shape. This paper also represents the Heart-shape which considered a special case of the X-shape. The system complexity has been measured by MLE and compared with V
Automatic RTL coding correction Linting tool for critical issues
This paper posits an automatic handling to some of the most common RTL critical issues in the verification process. In this paper, we propose an automatic linting tool to handle some causes of intentional latches generated in the synthesis process and clock gating timing violation. Therefore, no need to waste verification time to dive through long codes to handle them manually. The proposed tool
Band-Pass Filter and Relaxation Oscillator using Electric Double-Layer Capacitor
Supercapacitors are electrochemical devices that can store and restore electrical energy and are mostly used for powering dc or close-to-dc applications. As such they have not been explored enough for non-dc circuits. In this study, we implement a band-pass for frequency selectivity purposes and a relaxation oscillator for timing applications using a solid-state carbon electric double-layer
Two topologies of fractional-order oscillators based on CFOA and RC networks
This paper presents two general topologies of fractional order oscillators. They employ Current Feedback Op-Amp (CFOA) and RC networks. Two RC networks are investigated for each presented topology. The general oscillation frequency, condition and the phase difference between the oscillatory outputs are investigated in terms of the fractional order parameters. Numerical simulations and P-Spice
FPGA implementation of fractional-order Chua's chaotic system
This paper introduces FPGA implementation of fractional order double scrolls chaotic system based on Chua circuit. Grunwald-Letnikov's (GL) definition is used to generalize the chaotic system equations into the fractional-order domain. Xilinx ISE 14.5 is used to simulate the proposed design and Artix-7 XC7A100T FPGA is used for system realization. Experimental results are presented on digital
Simple MOS-based circuit designed to show pinched hysteresis behavior
We propose and validate a simple 3-transistor MOS circuit that shows an all-positive pinched hysteresis behavior. Complete analysis of the circuit is provided along with experimental results using a commercial CMOS transistor array. Copyright © 2018 John Wiley & Sons, Ltd.
Single active element implementation of fractional-order differentiators and integrators
A novel topology for implementing fractional-order differentiator and integrator transfer functions is presented in this paper. This topology is based on the employment of a second generation Current Conveyor with EXtra inputs (EX-CCII), passive resistors, and fractional-order capacitors. The main benefit offered by this implementation is that both fractional-order differentiator and integrator